1. Field of the Invention
The present invention relates to a display apparatus having an automatic quantization clock phase adjustment function, such as a projector and a monitor.
2. Description of the Related Art
Displaying an analog video signal showing documents, graphics and the like created by a computer on a display apparatus requires matching a quantization clock for the analog video signal and an effective image area of the analog video signal in the computer with those in the display apparatus. Such a display apparatus generally has a signal format table in which information on attributes of horizontal and vertical synchronization signals such as frequencies and polarities is correlated with the quantization clock and the effective image area. Reading such attributes of synchronization signals output from the computer enables discrimination of their signal formats.
The display apparatus normally generates the quantization clock needed for quantization of the analog video signal output from the computer by multiplication of the horizontal synchronization signal. An appropriate frequency of the quantization clock can be known from the above-described information of the synchronization signal. However, appropriate phases of the synchronization signals are different in respective computers. This is because the horizontal synchronization signal and the video signal output from the computer have a time difference, and the time differences are different in the respective computers.
Therefore, performing good quantization requires the display apparatus to have an automatic adjustment function of a phase of the quantization clock to compensate for the above-mentioned time difference. The phase of the quantization clock is hereinafter referred to as a “quantization clock phase” or a “clock phase”.
Japanese Patent Laid-Open No. 2000-122624 discloses an art relating to such automatic quantization clock phase adjustment. The disclosed art first detects video levels of an input analog video signal at a horizontal video start position (coordinates) and a horizontal video end position (coordinates) at each clock phase to combine the detected video levels at the same clock phase. This provides video level data that reflects a leading edge and a trailing edge of the input analog video signal. Then, the disclosed art regards a certain clock phase where the video level data becomes a maximum level as a stable phase where the video level is little changed, and fits the clock phase to be adjusted to the stable phase, thereby performing the automatic quantization clock phase adjustment.
On the other hand, Japanese Patent Laid-Open No. 11-177847 discloses the following art. The disclosed art first performs at each clock phase a process to obtain an absolute difference value of at least one pair of pixels adjacent to each other in one frame of an input video signal. Then, the disclosed art adjusts a frequency and a phase of the quantization clock such that the obtained absolute difference value becomes maximum.
However, the art disclosed in Japanese Patent Laid-Open No. 2000-122624 is based on a premise that levels of the leading edge and the trailing edge of the video signal respectively transit in a first half and a latter half of one quantization clock. Therefore, the disclosed art cannot be applied to a video signal that starts the level transitions of the leading edge and the trailing edge in an approximately same phase as shown in FIG. 13.
Moreover, the art disclosed in Japanese Patent Laid-Open No. 11-177847 is based on a premise that there are some image areas where an inclination of change of the video level is reversed at each pixel, and provides better adjustment accuracy as such image areas increase. Thus, in video signals often used for displaying presentation's titles which include few image areas where the inclination of the change of the video level is reversed at each pixel, the absolute difference value of the adjacent pixels is less changed even if the frequency and phase of the quantization are adjusted, and therefore the art cannot perform correct quantization clock phase adjustment.